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MT9075BPR Arkusz danych (PDF) - Zarlink Semiconductor Inc

MT9075BPR Datasheet PDF - Zarlink Semiconductor Inc
Numer części MT9075BPR
Pobierz  MT9075BPR Pobierz
Rozmiar pliku   866.59 Kbytes
Page   102 Pages
Producent  ZARLINK [Zarlink Semiconductor Inc]
Strona internetowa  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc
Szczegółowy opis E1 Single Chip Transceiver

MT9075BPR Datasheet (PDF)

Go To PDF Page Pobierz Arkusz danych
MT9075BPR Datasheet PDF - Zarlink Semiconductor Inc

Numer części MT9075BPR
Pobierz  MT9075BPR Click to download

Rozmiar pliku   866.59 Kbytes
Page   102 Pages
Producent  ZARLINK [Zarlink Semiconductor Inc]
Strona internetowa  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc
Szczegółowy opis E1 Single Chip Transceiver

MT9075BPR Arkusz danych (HTML) - Zarlink Semiconductor Inc


MT9075BPR Szczegóły Produktu

Description

The MT9075B is a single chip device which integrates an advanced PCM 30 framer with a Line Interface Unit (LIU). The framer interfaces to a 2.048 Mbit/s backplane and provides selectable rate data link access with optional HDLC controllers for S a bits and channel 16. The LIU interfaces the framer functions to the PCM 30 transformer-isolated four wire line. The MT9075B meets or supports the latest ITU-T Recommendations including G.703, G.704, G.706, G.732, G.775, G.796, G.823 for PCM 30, and I.431 for ISDN primary rate. It also meets or supports ETSI ETS 300 011, ETS 300 166 and ETS 300 233 as well as BS 6450.



Features

• Combined PCM 30 framer, Line Interface Unit (LIU) and link controllers in a 68 pin PLCC or 100 pin MQFP package

• Selectable bit rate data link access with optional S

a bits HDLC controller (HDLC0) and channel 16

HDLC controller (HDLC1)

• LIU dynamic range of 20 dB

• Enhanced performance monitoring and programmable error insertion functions

• Low jitter DPLL for clock generation

• Operating under synchronized or free run mode

• Two-frame receive elastic buffer with controlled slip direction indication

• Selectable transmit or receive jitter attenuator

• Intel or Motorola non-multiplexed parallel microprocessor interface

• CRC-4 updating algorithm for intermediate path points of a message-based data link application

• ST-BUS/GCI 2.048 Mbit/s backplane bus for both data and signalling



Applications

• E1 add/drop multiplexers and channel banks

• CO and PBX equipment interfaces

• Primary Rate ISDN nodes

• Digital Cross-connect Systems (DCS)




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