1FEATURES
2• 5 MHz–43 MHz Embedded Clock & DCBalanced
Data Transmission (21 Total LVDS
Data Bits Plus 3 Low Speed LVCMOS Data
Bits)
• User Adjustable Pre-Emphasis Driving Ability
Through External Resistor on LVDS Outputs
and Capable to Drive up to 10 Meters Shielded
Twisted-Pair Cable
• Supports AC-Coupling Data Transmission
• 100Ω Integrated Termination Resistor at LVDS
Input
• Power-Down Control
• Available @SPEED BIST to DS90UR124 to
Validate Link Integrity
• All LVCMOS Inputs & Control Pins Have
Internal Pulldown
• Schmitt Trigger Inputs on OS[2:0] to Minimize
Metastable Conditions
• Outputs Tri-Stated Through DEN
• On-Chip Filters for PLLs
• Power Supply Range 3.3V ± 10%
• Automotive Temperature Range −40°C to
+105°C
• Greater Than 8kV ESD Tolerance
• Meets ISO 10605 ESD and AEC-Q100
Compliance

DESCRIPTION
The DS99R421 converts a FPD-Link input with 4
non-DC Balanced LVDS (3 LVDS Data + LVDS
Clock) plus 3 over-sampled low speed control bits
into a single LVDS DC-balanced serial stream with embedded clock information. This single serial stream
simplifies transferring the 24-bit bus over a single
differential pair of PCB traces and cable by
eliminating the skew problems between the 3 parallel
LVDS data inputs and LVDS clock paths. It saves
system cost by narrowing 4 LVDS pairs to 1 LVDS
pair that in turn reduce PCB layers, cable width,
connector size, and pins.
The DS99R421 incorporates a single serialized LVDS
signal on the high-speed I/O. Embedded clock LVDS
provides a low power and low noise environment for
reliably transferring data over a serial transmission
path. By optimizing the converter output edge rate for
the operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost
signals over longer distances using lossy cables.
Internal DC balanced encoding is used to support
AC-Coupled interconnects.