FEATURES
· Operates From 1.65 V to 3.6 V
· Inputs Accept Voltages to 5.5 V
· Max tpd of 6.7 ns at 3.3 V
· Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
· Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
· Ioff Supports Partial-Power-Down Mode
Operation
· Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V VCC)
· Latch-Up Performance Exceeds 250 mA Per
JESD 17
· ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION
This 10-bit bus-interface D-type latch is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC841A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is
particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The ten latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true
data at its outputs.
A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.