• LP-HCSL outputs; save 4 resistors compared to standard
PCIe devices
• 23mW typical power consumption; reduced thermal
concerns
• OE# pins; support DIF power management
• Programmable Slew rate for each output; allows tuning
for various line lengths
• Programmable output amplitude; allows tuning for
various application environments
• DIF outputs blocked until PLL is locked; clean system
start-up
• Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
• External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
• Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
• Selectable SMBus addresses; multiple devices can
easily share an SMBus segment
• 3.3V tolerant SMBus interface works with legacy controllers
• Space saving 24-pin 4 x 4mm VFQFPN; minimal board space