▪ Eleven differential HCSL outputs
▪ One LVCMOS output; input reference can be bypassed to this output
▪ The clock input operates in full differential mode (LVDS,
LVPECL) or single-ended LVCMOS mode
▪ Driven from a crystal or differential clock input
▪ A 2.42.5GHz PLL frequency range supports Ethernet,
SONET, and CPRI frequency plans
▪ 1.25GHz maximum output frequency
▪ Four integer output dividers with a range of output divide ratios (see Table 5)
▪ One fractional output divider can generate any desired output frequency
▪ Support of output power-down
▪ Excellent clock output phase noise
Offset Output Frequency Single-side Band Phase Noise
100kHz 156.25MHz -143dBc/Hz
▪ Phase noise RMS, 156.25MHz, 12kHz to 20MHz integration
range: 80fs (typical)
▪ Selected configurations can be controlled via the use of control
input pins without need for serial port access
▪ LVCMOS compatible I2C serial interface gives access to
additional configurations by external processor or in
combination with the control input pins
▪ Single 3.3V supply voltage
▪ Lead-free (RoHS 6) 64-VFQFN packaging
▪ -40°C to 85°C ambient operating temperature