• External feedback path; Adjustable input-to-output delay
• 9 Selectable SMBus addresses/ Multiple devices can
share same SMBus segment
• 8 dedicated OE# pins/ hardware control of outputs
• PLL or bypass mode/ PLL can dejitter incoming clock
• Selectable PLL BW/ minimizes jitter peaking in
downstream PLL's
• Spread spectrum compatible/tracks spreading input clock
for EMI reduction
• SMBus Interface/ unused outputs can be disabled
• 100MHz & 133.33MHz PLL mode/ Legacy QPI support
• Undriven differential outputs in Power Down mode for maximum power savings