Description
The STPC Consumer-II integrates a standard 5th generation x86 core, a Synchronous DRAM controller, a graphics subsystem, a video pipeline, and support logic including PCI, ISA, and IDE controllers to provide a single consumer orientated PC compatible subsystem on a single device. The device is based on a tightly coupled Unified Memory Architecture (UMA), sharing memory between the CPU, the graphics and the video. The STPC Consumer-II is packaged in a 388 Plastic Ball Grid Array (PBGA). PBGA388 STPC Consumer II x86 Core Host I/F SDRAM CTRL SVGA GE VIP PCI m/s LB CTR PCI Bus ISA m/s IPC PCI m/s ISA Bus CRTC Cursor Monitor TV IDE I/F PMU Video Pipeline C Key K Key LUT Local Bus Encoder TVO JTAG