DSP56166ROM datasheet(46/63 Pages) MOTOROLA

46 / 63 page

PRELIMINARY - 6/15/93

MOTOROLA

DSP56166 Technical Data Sheet

NOTES:

1. “Host synchronization delay (tHSDL)” is the time period required for the DSP56166 to

sample any external asynchronous input signal, determine whether it is high or low, and

synchronize it to the internal clock.

2. See HOST PORT USAGE CONSIDERATIONS.

3. HREQ is pulled up by 1k

Ω.

4. Only if two consecutive reads from one of these registers are executed.

Num

Characteristic

60MHz

Unit

Min

Max

110

HR/W Low Setup Time Before HEN Asser-

tion

4—

111

HR/W Low Hold Time After HEN Deasser-

tion

4—

112

HR/W High Setup Time to HEN Assertion

—

113

HR/W High Hold Time After HEN/HACK

Deassertion

3—

114

HA0-HA2 Setup Time Before HEN Asser-

tion

0—

115

HA0-HA2 Hold Time After HEN Deassertion

—

116

DMA HACK Assertion to HREQ Deasser-

tion(see Note 3)

2T+

117

DMA HACK Deassertion to HREQ

Assertion(see Note 3)

for DMA RXL Read

for DMA TXL Write

for All Other Cases

tHSDL

+3T+4

tHSDL

+2T+4

—

118

Delay from HEN Deassertion to HREQ

Assertion for RXL Read (see Note 3)

tHSDL

+3T+4

—ns

119

Delay from HEN Deassertion to HREQ

Assertion for TXL Write (see Note 3)

tHSDL

+2T+4

—ns

120

Delay from HEN Assertion to HREQ Deas-

sertion for RXL Read, TXL Write

( see Note 3)

13.7

2T+

16.4

AC Electrical Characteristics — Host I/O Timing (Continued)

DSP56166ROM Arkusz danych(PDF) 46 Page - Motorola, Inc

DSP56166ROM Arkusz danych(HTML) 46 Page - Motorola, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Arkusz danych Pobierz

Link URL