SLG46127 datasheet(2/88 Pages) DIALOG

2 / 88 page

000-0046127-101

Page 1 of 87

SLG46127

1.0 Overview

The SLG46127 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit

design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macro

cells of the SLG46127. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very

small, low power single integrated circuit. The SLG46127 includes the following:

• Two Analog Comparators (ACMP)

• Four Combinatorial Look Up Tables (LUTs)

• Two 2-bit LUTs

• Two 3-bit LUTs

•

Six Combination Function Macro cell

• Two Selectable DFF/Latch or 2-bit LUTs

• Two Selectable DFF/Latch or 3-bit LUTs

• One Selectable Pipe Delay or 3-bit LUT

• Pipe Delay – 8 stage / 2 output

• One Selectable Counter/Delay or 4-bit LUT

•

Three Counter / Delay Generators (CNT/DLY)

• Three 8-bit counter/delays with external clock/reset

•

Programmable Delay

•

One Logic Function – 1 Deglitch Filter

•

RC Oscillator (RC OSC)

•

Power On Reset (POR)

•

P-FET Power Switch

• Power Switch IDS: 2 A

• VIN: 1.71 V to 5.5 V

• Low RDSON

•44 m

 @ 5.5 V

•58 m

 @ 3.3 V

•110 m

 @ 1.71 V

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