CY8C52LP datasheet(33/114 Pages) CYPRESS

33 / 114 page

PSoC® 5LP: CY8C52LP Family

Datasheet

Document Number: 001-84933 Rev. *L

Page 33 of 114



USBIO features:



Full speed USB 2.0 compliant I/O



Highest drive strength for general purpose use



Input, output, or both for CPU and DMA



Input, output, or both for digital peripherals



Digital output (CMOS) drive mode



Each pin can be an interrupt source configured as rising

edge, falling edge, or both edges

Figure 6-9. GPIO Block Diagram

Drive

Logic

PRT[x]DM0

PRT[x]DR

Digital Output Path

Digital Input Path

PRT[x]SLW

LCD

Logic & MUX

PRT[x]DM1

PRT[x]DM2

PRT[x]LCD_EN

PRT[x]LCD_COM_SEG

Analog

Analog Mux

Analog Global

Digital System Output

PRT[x]BYP

PRT[x]BIE

Bidirectional Control

Capsense Global Control

Switches

Pin Interrupt Signal

Digital System Input

PRT[x]PS

PRT[x]CTL

Input Buffer Disable

Display

Data

Interrupt

Logic

PICU[x]INTTYPE[y]

PICU[x]INTSTAT

Vddio

Vddio Vddio

Slew

Cntl

LCD Bias Bus

PRT[x]AMUX

PRT[x]AG

CAPS[x]CFG1

PRT[x]SYNC_OUT

PRT[x]DBL_SYNC_IN

PICU[x]INTSTAT

Naming Convention

‘x’ = Port Number

‘y’ = Pin Number

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