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TCD2000P Arkusz danych(PDF) 2 Page - Toshiba Semiconductor |
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TCD2000P Arkusz danych(HTML) 2 Page - Toshiba Semiconductor |
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2 / 11 page ![]() TCD2000P 2002-03-08 2 CIRCUIT DIAGRAM PIN NAMES φM Master Clock VAD Power (Analog) φ1 Clock (Phase 1) VDD1 Power (Digital, 12V) φ2 Clock (Phase 2) VDD2 Power (Digital, 12V) SH Shift Gate SS Ground (Analog) OS Signal Output SS1 Ground (Digital, 12V) DOS Compensation Output SS2 Ground (Digital, 12V) VREF Reference Voltage Input VSP Sample and Hold Switch NC Non Connection |
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