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MP8712 Arkusz danych(PDF) 21 Page - Monolithic Power Systems

Numer części MP8712
Szczegółowy opis  High-Efficiency, 12A, 3V-18V, Synchronous Step-Down Converter with Power Good, External Soft Start and OVP
PDF  26 Pages
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Producent  MPS [Monolithic Power Systems]
Strona internetowa  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP8712 Arkusz danych(HTML) 21 Page - Monolithic Power Systems

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MP8712 – 18V, 12A, SYNCHRONOUS STEP-DOWN CONVERTER
MP8712 Rev.1.0
www.MonolithicPower.com
21
3/28/2017
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
PCB Layout Guidelines (8)
Efficient PCB layout is critical for stable
operation. A four-layer layout is strongly
recommended
to
achieve
better
thermal
performance. For best results, refer to Figure 7
and follow the guidelines below.
1. Place the high current paths (PGND, VIN,
and SW) very close to the device with short,
direct, and wide traces.
2. Keep the VIN and PGND pads connected
with large coppers.
3. Use at least two layers for the VIN and
PGND trace to achieve better thermal
performance.
4. Add several vias close to the VIN and
PGND pads to help with thermal dissipation.
5. Place the input capacitors as close to VIN
and PGND as possible.
6. Place the decoupling capacitor as close to
VCC and PGND as possible.
7. Place the external feedback resistors next
to FB.
8. Ensure that there is no via on the FB trace.
9. Keep the switching node (SW) short and
away from the feedback network.
10. Keep the BST voltage path (BST, C3, and
SW) as short as possible.
NOTE:
8)
The recommended layout is based on the Typical
Application Circuits on page 22 to page 25.
Figure 7: Recommended Layout
Design Example
Table 2 is a design example following the
application guidelines for the specifications.
Table 2: Design Example
VIN
12V, 3V
VOUT
1V
IOUT
12A
The detailed application schematics are shown
in Figure 8 through Figure 17. The typical
performance and circuit waveforms are shown
in the Typical Performance Characteristics
section. For more device applications, please
refer to the related evaluation board datasheets.



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