Rev. 1.0

Page 2 of 12

www.sitime.com

The Smart Timing Choice



The Smart Timing Choice



SiT2002B

High Frequency, Single Chip, One-output Clock Generator

GND

1

NC

2

OE/ST/NC

3

VDD

4

OUT

5

Notes:

1. In OE or ST mode, a pull-up resistor of 10 kΩ or less is recommended if pin 3 is not externally driven.

If pin 3 needs to be left floating, use the NC option.

2. A capacitor of value 0.1 µF or higher between Vdd and GND is required.

Table 1. Electrical Characteristics (continued)

Parameters

Symbol

Min.

Typ.

Max.

Unit

Condition

Startup and Resume Timing

Startup Time

T_start

–

–

5

ms

Measured from the time Vdd reaches its rated minimum value

Enable/Disable Time

T_oe

–

–

130

ns

f = 115 MHz. For other frequencies, T_oe = 100 ns + 3 * clock

periods

Resume Time

T_resume

–

–

5

ms

Measured from the time ST pin crosses 50% threshold

Jitter

RMS Period Jitter

T_jitt

–

1.9

3

ps

f = 125 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V

–

1.6

4

ps

f = 125 MHz, Vdd = 1.8V

Peak-to-peak Period Jitter

T_pk

–

12

20

ps

f = 125 MHz, Vdd = 2.5V, 2.8V, 3.0V or 3.3V

–

14

30

ps

f = 125 MHz, Vdd = 1.8V

RMS Phase Jitter (random)

T_phj

–

0.5

0.9

ps

Integration bandwidth = 900 kHz to 7.5 MHz

–1.3

2

ps

Integration bandwidth = 12 kHz to 20 MHz

Table 2. Pin Description

Pin

Symbol

Functionality

1

GND

Power

Electrical ground

2

NC

No Connect

No connect

3OE/ ST/NC

Output

Enable

L: output is high impedance. Only output driver is disabled.

Standby

L: output is low (weak pull down). Device goes to sleep mode. Supply

current reduces to I_std.

No Connect

output. Pin 3 has no function.

4

VDD

Power

5

OUT

Output

Oscillator output

Top View

Figure 1. Pin Assignments