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1.0 CONNECTION DIAGRAMS

Order Number SC14405AFLAG (128kbyte Full FLASH , Boot mode A, 100 pins TQFP)

Order Number SC14405AFLBG (128kbyte Full FLASH , Boot mode B, 100 pins TQFP)

Order Number SC14405AxxAG (128kbyte ROM FLASH , Boot mode A, 100 pins TQFP)

Order Number SC14405AxxBG (128kbyte ROM FLASH , Boot mode B, 100 pins TQFP)

See NS Package Number VJG100A

Note 1:

All digital outputs can sink/source 2 mA unless otherwise specified. All digital inputs are Schmitt trigger types. After reset all I/Os are set to input

and all pull-up or pull-down resistors are enabled unless otherwise specified.

PU = Pull-up resistor enabled, PD = Pull-down resistor enabled, I = input

A-I, B-I = In Boot mode A or B input and pull-up or pull-down resistor disabled,

A-PD, B-PU = In Boot mode A, Pull-down resistor enabled. In Boot mode B, pull-up resistor enabled.

Note 2:

Reset state of address and data bus and WRn, RDn pins:

if SC14405: All signals are ‘1’ at startup.

AD0

AD1

AD2

AD3

RSTN

AVS2

LRS+

AVD

VDDRF

LRS-

VREF-

MIC-

AGND

MIC+

VREF+

VBAT1

VBAT2

VBAT3

DC_stab

LDO1_CTRL

DC_I

AVS

AD18

CAP

DAC

PD7

PD1

PD5

PD4

PD3

PD2

Xtal1

RFCLK

RSSI

PCM_FSC/PD6/ADC3

PCM_CLK/DAC2/ADC2

VSS

SK

SO

TDO

CMPREF

RDI

LE

VDD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

SC14405

AVD2

DC_Sense

LDO_Sense

LDO2_CTRL

DAB0

DAB1

17-12-1998

P2[6]

DC_DIS

LCD26/BP3

BP2

BP1

BP0

LCD25/BP4

LCD24

LCD0

P3[0]

P3[1]