SN74GTLP2033

8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER

WITH SPLIT LVTTL PORT AND FEEDBACK PATH

SCES352C – JUNE 2001 – REVISED SEPTEMBER 2001

3

POST OFFICE BOX 655303

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

TSSOP – DGG

Tape and reel

SN74GTLP2033DGGR

GTLP2033

–40

°C to 85°C

TVSOP – DGV

Tape and reel

SN74GTLP2033DGVR

GT2033

VFBGA – GQL

Tape and reel

SN74GTLP2033GQLR

GR033

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

functional description

The SN74GTLP2033 is a high-drive (100 mA), 8-bit, three-wire registered transceiver containing D-type latches

and D-type flip-flops for data-path operation in the transparent, latched, or flip-flop modes. Data transmission

is complementary, with inverted AI data going to the B port and inverted B data going to AO. The split LVTTL

AI and AO provides a feedback path for control and diagnostics monitoring.

The logic element for data flow in each direction is configured by two mode (IMODE1 and IMODE0 for B to A,

OMODE1 and OMODE0 for A to B) inputs as a buffer, D-type flip-flop, or D-type latch. When configured in the

buffer mode, the inverted input data appears at the output port. In the flip-flop mode, data is stored on the rising

edge of the appropriate clock (CLKAB/LEAB or CLKBA/LEBA) input. In the latch mode, the clock inputs serve

as active-high transparent latch enables.

Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the

LOOPBACK input. When LOOPBACK is low, B-port data is the B-to-A input. When LOOPBACK is high, the

output of the selected A-to-B logic element (prior to inversion) is the B-to-A input.

is in the high-impedance state. When OEBA is high, AO is active (high or low logic levels).

is inactive. If OEAB is high and OEAB is low, the B port is active.

The A-to-B and B-to-A logic elements are active, regardless of the state of their associated outputs. The logic

elements can enter new data (in flip-flop and latch modes) or retain previously stored data while the associated

outputs are in the high-impedance (AO) or inactive (B port) states.