MP4051—NON-ISOLATED OFFLINE LED CONTROLLER WITH ACTIVE PFC

MP4051 Rev. 1.01

www.MonolithicPower.com

11

1/21/2014

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Power Factor Correction

The MULT pin is connected to the tap of the

resistor divider from the rectified instantaneous

line voltage and fed as one input of the Multiplier.

The output of the multiplier will be shaped as

sinusoid too. This signal provides the reference

for the current comparator and comparing with

the inductor current which sets the inductor peak

current shaped as sinusoid with the input line

voltage. High power factor can be achieved.

Inductor current

Multiplier output

Figure 4—Power Factor Correction Scheme

The maximum voltage of the multiplier output to

the current comparator is clamped to 2.5V to get

a cycle-by-cycle current limitation.

VCC Under-voltage Lockout

When the VCC voltage drops below UVLO

threshold 9V, the MP4051 stops switching and

totally shuts down, the VCC will restart charging

by the external start up resistor from AC line.

Figure 5 shows the typical waveform of VCC

under-voltage lockout

13.6V

9V

Vcc

Gate

Switching Pulses

And Regulates the VCC

Auxiliary Winding Takes Charge

Protection happens

Figure 5—VCC Under-Voltage Lockout

Auto Starter

The MP4051 integrates an auto starter, the

starter starts timing when the MOSFET is turned

off, if ZCD fails to send out another turn on signal

after 130µs, the starter will automatically send

out the turn on signal which can avoid the IC

unnecessary shut down by ZCD missing

detection.

Minimum Off Time

The MP4051 operates with variable switching

frequency, the frequency is changing with the

input instantaneous line voltage. To limit the

maximum frequency and get a good EMI

performance, MP4051 employs an internal

minimum off time limiter—3.5µs, show as Figure

6.

ZCD

GATE

3.5us

Figure 6—Minimum Off Time

Leading Edge Blanking

In order to avoid the premature termination of the

switching pulse due to the spike at MOSFET

turning on, an internal leading edge blanking

(LEB) unit is employed between the CS Pin and

the current comparator input. During the blanking

time, the path, CS Pin to the current comparator

input, is blocked. Figure 7 shows the leading

edge blanking.

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Figure 7—Leading Edge Blanking