MP8763DGL datasheet(19/25 Pages) MPS

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MP8763D ― 12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER

MP8763D Rev. 1.1

www.MonolithicPower.com

1/15/2015

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

APPLICATION INFORMATION

Setting

the

Output

Voltage-Large

ESR

Capacitors

For applications that electrolytic capacitor or POS

capacitor with a large ESR is set as output

capacitors. The feedback resistors—R1 and R2

as shown in Figure 10—set the output voltage.

ESR

POSCAP

VOUT

Figure10—Simplified POSCAP Circuit

First, choose a value for R2 that balances

between high quiescent current loss (low R2) and

high noise sensitivity on FB (high R2). A typical

value falls within 5kΩ to 50kΩ, using a

comparatively larger R2 when VOUT is low, and a

smaller R2 when VOUT is high. Then calculate R1

as follows, which considers the output ripple:

OUT

REF

−× Δ

−

=×

(15)

Where

OUT

is the output ripple determined by

equation 24.

Setting

the

Output

Voltage-Small

ESR

Capacitors

Ceramic

VOUT

Figure11—Simplified Ceramic Capacitor

Circuit

When using a low ESR ceramic capacitor on the

output,

add

external

voltage

ramp

to the FB pin consisting of R4 and C4.The ramp

voltage, VRAMP, and the resistor divider influence

the output voltage as shown in Figure 11.

Calculate VRAMP as shown in equation 7. Select

R2 to balance between high quiescent current

loss and FB noise sensitivity. Choose R2 within

5kΩ to 50kΩ, using a larger R2 when VOUT is low,

and a smaller R2 when VOUT is high. Determine

the value of R1 as follows:

)

AVG

(

OUT

)

AVG

(

−

(16)

Where VFB(AVG) is the average FB voltage. VFB(AVG)

varies with the VIN, VOUT, and load condition,

where the load regulation is strictly related to the

VFB(AVG). Also the line regulation is related to the

VFB(AVG); improving the load or line regulation

involves a lower VRAMP that meets equation 9.

For PWM operation, estimate VFB(AVG) from

equation 17.

FB( AVG)

REF

RAMP

=+ ×

(17)

Usually, R9 is 0Ω, though it can also be set

following equation 18 for better noise immunity. It

should also be less than 20% of R1//R2 to

minimize its influence on VRAMP.

1R1 R2

5R1 R2

<×

(18)

Using equations 16 and 17 to calculate the

output voltage can be complicated. To simplify

the R1 calculation in equation 16, add a DC-

blocking capacitor, CDC, to filter the DC influence

from R4 and R9. Figure 12 shows a simplified

circuit with external ramp compensation and a

DC-blocking capacitor. The addition of this

capacitor, simplifies the R1 calculation as per

equation 19 for PWM mode operation.

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