LTC6652 datasheet(41/50 Pages) LINER

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LTC2373-18

237318f

For more information www.linear.com/LTC2373-18

RESET Timing

When the RESET pin is high, the LTC2373-18 is reset and

the serial I/O data bus is put into a high impedance mode,

as shown in Figure 29. The serial data output register and

sequencer memory are also cleared and set to their default

states. If this occurs during a conversion, the conversion

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Figure 29. RESET Pin Timing

is immediately halted. During reset, requests for new

conversions are ignored. Once RESET returns low, the

LTC2373-18 is ready to start a new conversion after the

acquisition time has been met.

To obtain the best performance from the LTC2373-18

a printed circuit board is recommended. Layout for the

printed circuit board (PCB) should ensure the digital and

analog signal lines are separated as much as possible.

In particular, care should be taken not to run any digital

clocks or signals alongside analog signals or underneath

the ADC.

Recommended Layout

ThefollowingisanexampleofarecommendedPCBlayout.

A single solid ground plane is used. Bypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

ADC. The analog input traces are screened by ground.

For more details and information refer to DC2071, the

evaluation kit for the LTC2373-18.

237318 F29

RESET

CNV

SDO

tRESETH

tACQ

Hi-Z

LTC6652 Arkusz danych(PDF) 41 Page - Linear Technology