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LTC2335-18

233518f

For more information www.linear.com/LTC2335-18

applicaTions inForMaTion

24ns implies an 18-bit settling time to a full-scale step of

approximately13 • (RIN • CIN) = 312ns.Theimpedanceand

self-settling of external circuitry connected to the analog

input pins will increase the overall settling time required.

Low impedance sources can directly drive the inputs of

the LTC2335-18 without gain error, but high impedance

sources should be buffered to ensure sufficient settling

during acquisition and to optimize the linearity and distor-

tion performance of the ADC. Settling time is an important

consideration even for DC input signals, as the voltages on

the sampling capacitors will differ from the analog input

pin voltages at the start of acquisition.

Mostapplicationsshoulduseabufferamplifiertodrivethe

analog inputs of the LTC2335-18. The amplifier provides

low output impedance, enabling fast settling of the analog

signal during the acquisition phase. It also provides isola-

tion between the signal source and the charge flow at the

analog inputs when entering acquisition.

Input Filtering

The noise and distortion of an input buffer amplifier and

other supporting circuitry must be considered since they

add to the ADC noise and distortion. Noisy input signals

should be filtered prior to the buffer amplifier with a low-

bandwidth filter to minimize noise. The simple one-pole

RC lowpass filter shown in Figure 5 is sufficient for many

applications.

At the output of the buffer, a lowpass RC filter network

formed by the 600Ω sampling switch on-resistance (RIN)

and the 40pF sampling capacitance (CIN) limits the input

bandwidth on each channel to 7MHz, which is fast enough

to allow for sufficient transient settling during acquisition

while simultaneously filtering driver wideband noise.

A buffer amplifier with low noise density should be se-

lected to minimize SNR degradation over this bandwidth.

An additional filter network may be placed between the

buffer output and ADC input to further minimize the noise

other. Traditional examples include fully differential input

signals, where IN+ and IN– are driven 180 degrees out-of-

phasewithrespecttoeachothercenteredaroundacommon

mode voltage (VIN+ + VIN–)/2,andpseudo-differentialtrue

bipolar input signals, where IN+ swings above and below

a ground reference level, driven on IN–. Regardless of the

chosen SoftSpan range, the wide common mode input

range and high CMRR of the IN+/IN– analog inputs allow

them to swing with an arbitrary relationship to each other,

provided each pin remains between (VCC – 4V) and VEE.

The output data format for all bipolar SoftSpan ranges is

two’s complement.

Unipolar SoftSpan Input Ranges

For conversions configured in SoftSpan ranges 5, 4, 1,

or 0, the LTC2335-18 digitizes the differential analog

input voltage (VIN+ – VIN–) over a unipolar span of 0V

to 2.5 • VREFBUF, 0V to 2.5 • VREFBUF/1.024, 0V to 1.25 •

VREFBUF, or 0V to 1.25 • VREFBUF/1.024, respectively, as

shown in Table 1a. These SoftSpan ranges are useful for

digitizing input signals where IN+ remains above IN–. A

traditional example includes pseudo-differential unipolar

input signals, where IN+ swings above a ground reference

level, driven on IN–. Regardless of the chosen SoftSpan

range, the wide common mode input range and high

CMRR of the IN+/IN– analog inputs allow them to swing

with an arbitrary relationship to each other, provided each

pin remains between (VCC – 4V) and VEE. The output data

format for all unipolar SoftSpan ranges is straight binary.

INPUT DRIVE CIRCUITS

The initial voltage on each channel’s sampling capacitors

at the start of acquisition must settle to the new input

pin voltages during the acquisition interval. The external

circuitry connected to IN+ and IN– must source or sink

the charge that flows through RIN as this settling occurs.

The LTC2335-18 sampling network RC time constant of

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