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STR710FZ1T6 Arkusz danych(PDF) 13 Page - STMicroelectronics |
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STR710FZ1T6 Arkusz danych(HTML) 13 Page - STMicroelectronics |
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13 / 49 page ![]() STR71xF - INTRODUCTION 13/49 40 K3 V33IO-PLL S Supply voltage for digital I/O circuitry and for PLL refer- ence 41 M2 N.C. Not connected (not bonded) 42 L4 VSSIO-PLL S Ground voltage for digital I/O circuitry and for PLL ref- erence 43 M4 N.C. Not connected (not bonded) 44 M3 DBGRQS I CT Debug Mode request input (active high) 45 K4 CKOUT O 8mA X Clock output (fPCLK2) Note: Enabled by CKDIS register in APB Bridge 2 46 J4 CK I C Reference clock input 47 M5 P0.15/WAKE- UP Ipu TT X4mA X Port 0.15 Wakeup from Standby mode input. 48 L5 N.C. Not connected (not bonded) 49 K5 RTCXTI Realtime Clock input and input of 32 kHz oscillator am- plifier circuit 50 J5 RTCXTO Output of 32 kHz oscillator amplifier circuit 51 M6 STDBY I/O CT 4mA X X Input: Hardware Standby mode entry input active low. Caution: External pull-up to V33 required to select nor- mal mode. Output: Standby mode active low output following Soft- ware Standby mode entry. Note: In Standby mode all pins are in high impedance except those marked Active in Stdby 52 M7 RSTIN ICT X Reset input 53 J6 N.C. Not connected (not bonded) 54 L6 VSSBKP S X Stabilisation for low power voltage regulator. 55 K6 V18BKP SX Stabilisation for low power voltage regulator. Requires external capacitors of at least 1µF between V18BKP and VSS18BKP. See Figure 5. Note: If the low power voltage regulator is bypassed, this pin can be connected to an external 1.8V supply. 56 H5 N.C. Not connected (not bonded) 57 H6 N.C. Not connected (not bonded) 58 G6 V18 S Stabilisation for main voltage regulator. Requires exter- nal capacitors of at least 10µF + 33nF between V18 and VSS18. See Figure 5. 59 L7 VSS18 S Stabilisation for main voltage regulator. 60 K7 N.C. Not connected (not bonded) Table 3. STR710 Pin Description Pin n° Pin Name Input Output Main function (after reset) Alternate function |
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