PC7447 datasheet(21/66 Pages) ATMEL

21 / 66 page

PC7457/47 [Preliminary]

5345B–HIREL–02/04

Notes:

1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus) fre-

quency, CPU (core) frequency and PLL (VCO) frequency don’t exceed their respective maximum or minimum operating

frequencies. Refer to the PLL_CFG[0:4] signal description in “PLL Configuration” on page 51 for valid PLL_CFG[0:4]

settings

2. Assumes lightly-loaded, single-processor system.

3. Rise and fall times for the SYSCLK input measured from 0.4V to 1.4V.

4. Timing is guaranteed by design and characterization.

5. This represents total input jitter, short-term and long-term combined, and is guaranteed by design.

6. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at -20 dB. The bandwidth must be set low to allow

cascade connected PLL-based devices to track SYSCLK drivers with the specified jitter.

7. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for

PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies

when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held

asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.

Figure 8 provides the SYSCLK input timing diagram.

Figure 8. SYSCLK Input Timing Diagram

VM = Midpoint Voltage (OV

DD/2)

SYSCLK

tKHKL

tSYSCLK

CVIL

CVIH

tKR

tKF

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