ISL97635A datasheet(13/29 Pages) RENESAS

13 / 29 page

ISL97635A

FN6564 Rev.3.00

Page 13 of 29

Sep 26, 2017

For example, if PWMO is applied with a DC voltage

1.21V, the

output will be zero. On the other hand, if the PWMO is applied

with a DC voltage

 0.21V, the PWM duty cycle will be at its

maximum. If the PWMO pin is applied with a DC voltage of 0.31V,

the PWM duty cycle will be at 90% at 200Hz if CFPWM = 27nF.

PWM Dimming Frequency Adjustment

(Applicable to SMBus controlled PWM, DPST,

and DC-to-PWM Modes)

Except for the external PWM dimming mode where the frequency

follows the external signal’s, the dimming frequencies of the

other modes are set by an external capacitor CFPWM at the FPWM

pin as shown in Equation 12:

where FPWM is the desirable PWM dimming frequency.

For example, if FPWM = 200Hz, CFPWM = 5.4µ/200 = 27nF

The PWM dimming frequency can be for example 20kHz but

there are a minimum on and off time requirements such that the

dimming will be in the range of 10% to 99.5%. If the dimming

frequency is below 5kHz, the dimming range can be 1% to

99.5%.

In the DPST and DC-to-PWM modes, a CPWMO capacitor is also

needed. An internal 40kΩ and an external CPWMO at the PWMO

pin form a low pass network to filter the PWMI to an averaged

DC. As a result, the time constant of the 40kΩ and CPWMO should

be significantly larger than the external PWMI period, t, such

that:

For example, if FPWM is 200Hz and external PWMI is 1kHz or

above, a 220nF CPWMO can be chosen that allows the external

PWMI signal to be filtered as an averaged DC. Also, the FPWM

frequency in the DPST mode should be limited between 100Hz to

2kHz and at least five times smaller than the external PWMI

frequency when DPST mode is used.

Switching Frequency

An internal clock of 1.2MHz is used for the boost regulator

control of the LX pin in default. There are 2 levels of switching

frequencies: 600kHz or 1.2MHz. Each can be programmed in the

Configuration Register 0x08 bit 2. The default switching

frequency is at 1.2MHz.

5V Low Dropout Regulator

A 5.2V LDO regulator is present at the VDC pin to develop the

necessary low voltage supply which is used by the chips internal

control circuitry. Because VDC is an LDO pin, it requires a bypass

capacitor of 1µF or more for the regulation. For applications with

an input voltage

 5.5V, the VIN and VDC pins can be connected

together. The VDC pin can be used as a coarse reference with few

mA sourcing capability.

In-rush Control and Soft-start

The ISL97635A has separately built-in independent inrush

control and soft-start functions. The inrush control function is

built around the short-circuit protection FET, and is only available

in applications which include this device. At start-up, the fault

protection FET is turned on slowly due to a 30µA pull-down

current output from the FAULT pin. This discharges the fault FET's

gate-source capacitance, turning on the FET in a controlled

fashion. As this happens, the output capacitor is charged slowly

through the weakly turned on FET before it becomes fully

enhanced. This results in a low in-rush current. This current can

be further reduced by adding a capacitor (in the 1nF to 5nF

range) across the gate-source terminals of the FET.

Once the chip detects that the fault protection FET is turned on

hard, it is assumed that inrush is complete. At this point, the

boost regulator will begin to switch and the current in the

inductor will ramp-up. The current in the boost power switch is

monitored and the switching terminated in any cycle where the

current exceeds the current limit. The ISL97635A includes a soft-

start feature where this current limit starts at a low value

(375mA). This is stepped up to the final 3A current limit in seven

further steps of 375mA. These steps will happen over a 1ms total

time, such that after 1ms the final limit will be reached. This

allows the output capacitor to be charged to the required value at

a low current limit and prevents high input current for systems

that have only a low to medium output current requirement.

For systems with no master fault protection FET, the in-rush

current will flow towards COUT when VIN is applied and it is

determined by the ramp rate of VIN and the values of COUT and L.

Fault Protection and Monitoring

The ISL97635A features extensive protection functions to cover

all the perceivable failure conditions. The failure mode of a LED

can be either open circuit or as a short. The behavior of an open

circuited LED can additionally take the form of either infinite

resistance or, for some LEDs, a zener diode, which is integrated

into the device in parallel with the now opened LED.

For basic LEDs (which do not have built-in zener diodes), an open

circuit failure of an LED will only result in the loss of one channel

of LEDs without affecting other channels. Similarly, a short-circuit

condition on a channel that results in that channel being turned

off does not affect other channels unless a similar fault is

occurring. All LED faults are reported via the SMBus interface to

determine which channels have failed via register 0x09 (Output

masking register). The controller can also choose to use register

0x09 to disable faulty channels at start-up, resulting in only

further faulty channels being reported by register 0x02.

Due to the lag in boost response to any load change at its output,

certain transient events (such as LED current steps or significant

step changes in LED duty cycle) can transiently look like LED

fault modes. The ISL97635A uses feedback from the LEDs to

determine when it is in a stable operating region and prevents

apparent faults during these transient events from allowing any

of the LED stacks to fault out. See Table 1 for more details.

A fault condition that results in an input current that exceeds the

devices electrical limits will result in a shutdown of all output

channels. The control device logic will remain functional such

that the Fault/Status Register can be interrogated by the system.

The root cause of the failure will be loaded to the volatile

CFPWM

5.4

 F

PWM



(EQ. 12)

40k

 x C

PWMO>t

(EQ. 13)

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