ADL5202ACPZ-R7 datasheet(16/29 Pages) AD

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ADL5202

Data Sheet

Rev. D | Page 16 of 29

THEORY OF OPERATION

DIGITAL INTERFACE OVERVIEW

The ADL5202 VGA has three digital gain control options:

the parallel control interface, serial peripheral interface, and gain

up/down interface. The desired gain control option is selected

via two control pins, MODE0 and MODE1 (see Table 4 for the

truth table for the mode control pins). The gain code is in a 6-bit

binary format. A voltage of between 1.4 V and 3.3 V is required

for a logic high.

Three pins are common to all gain control options: PM, PWUPA,

and PWUPB. PM allows the user to choose operation in nominal

mode or high performance mode. PWUPA and PWUPB are

power-up pins for Channel A and Channel B, respectively.

Physical pins are shared among the three interfaces, resulting in

as many as three different functions per digital pin (see Table 3).

Table 4. Digital Control Interface Selection Truth Table

MODE1

MODE0

Interface

Parallel control

Serial peripheral (SPI)

Up/down

PARALLEL DIGITAL INTERFACE

The parallel digital interface uses six binary bits (Bits[A5:A0] or

Bits[B5:B0]) and a latch pin (LATCHA or LATCHB) per amplifier.

The latch pin controls whether the input data latch is transparent

or latched. In transparent mode, gain changes as input gain control

bits change. In latched mode, gain is determined by the latched

gain setting and does not change with changing input gain

control bits.

SERIAL PERIPHERAL INTERFACE (SPI)

The SPI uses three pins (SDIO, SCLK, and CSA or CSB). The

SPI data register consists of two bytes: six gain control bits, two

attenuation step size address bits, one read/write bit, and seven

don’t care bits. SDIO is the serial data input and output pin. The

SCLK pin is the serial clock, and CSA or CSB is the channel

select pin.

DATA

READ/WRITE

DO NOT CARE

(7 BITS)

FAST ATTACK ATTENUATION

STEP SIZE ADDRESS

GAIN CONTROL

FA0 FA1 R/W DNC DNC DNC DNC DNC DNC DNC

LSB

MSB

Figure 50. 16-Bit SPI Register

To write to the SPI register, CSA or CSB must be pulled low and

16 clock pulses must be applied to SCLK. Individual channel

SPI registers can be selected by pulling CSA or CSB low. By

pulling the CSA and CSB pins low simultaneously, the same

data can be written to both SPI registers.

To read the SPI register value, the R/W bit must be set high,

CSA or CSB must be pulled low, and the part must be clocked.

After the register has been read out during the next 16 clock cycles,

the SPI is automatically put into write mode. Note that there is

only one SDIO pin. Readback from the registers should be per-

formed individually.

Fast Attack

The fast attack feature, accessible via the SPI, allows the gain to be

reduced from its present gain setting by a predetermined step size.

Four different attenuation step sizes are available. The truth table

for fast attack is shown in Table 5.

Table 5. SPI 2-Bit Attenuation Step Size Truth Table

FA1

FA0

Step Size (dB)

SPI fast attack mode is controlled by the FA_A or FA_B pin.

A logic high on the FA_A or FA_B pin results in an attenuation

that is selected by Bits[FA1:FA0] in the SPI register.

GAIN UP/DOWN INTERFACE

The GS1 and GS0 pins control the up/down gain step function.

Gain is increased by a clock pulse on the UPDN_CLK_A pin or

the UPDN_CLK_B pin (rising and falling edges) when the

UPDN_DAT_A or UPDN_DAT_B pin is high. Gain is decreased

by a clock pulse on the UPDN_CLK_A or UPDN_CLK B pin

when the UPDN_DAT_A or UPDN_CLKB pin is low. The truth

table for the gain step function is shown in Table 6. Reset is

detected by a rising edge latching data having one polarity, with

the falling edge latching the opposite polarity. Reset results in

a minimum binary gain code of 111111.

Table 6. Step Size Control Truth Table

GS1

GS0

Step Size (dB)

0.5

The step size is selectable using the GS1 and GS0 pins. The gain

is limited by the top and bottom of the control range.

RESET

UPDN_DAT

UPDN_CLK

Figure 51. Up/Down Timing

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