PC87322VF datasheet(8/84 Pages) NSC

8 / 84 page

10 Pin Description (Continued)

Symbol

Function

DIR

Direction

This output determines the direction of the floppy disk drive (FDD) head movement (active

step in inactive e step out) during a seek operation During read or writes DIR will be inactive

Direction

This pin provides an additional direction signal in PPM Mode when PNFe0 (See INIT and

Table 7-5 for further information)

DR01

44 45

Drive Select 01

These are the decoded drive select outputs that are controlled by Digital Output

outputs They are encoded with information to control four FDDs when bit 4 of the Function Enable

DR1 when bit 4 of Function Control Register (FCR) is set (See Table 7-5 for further information)

Drive Select 1

This pin provides an additional Drive Select signal in PPM Mode when PNFe0 It is

drive select 1 when bit 4 of FCR is 0 It is drive select 0 when bit 4 of FCR is 1 This signal is active low

(See ACK and Table 7-5 for further information)

DRATE01

52 51

Data Rate 01

These outputs reflect the currently selected FDC data rate (bits 0 and 1 in the

Configuration Control Register (CCR) or the Data Rate Select Register (DSR) whichever was written

to last) These pins are totem-pole buffered outputs (6 mA sink 6 mA source)

DRQ

DMA Request

Active high output to signal the DMA controller that a FDC data transfer is needed

When in PC-AT or Model 30 mode this signal is enabled by bit D3 of the DOR When in PS2 mode

DRQ is always enabled and bit D3 of the DOR is reserved

DRV2

Drive2

This input indicates whether a second disk drive has been installed The state of this pin is

available from Status Register A in PS2 mode (See PNF for further information)

DSKCHG

Disk Change

The input indicates if the drive door has been opened The state of this pin is available

from the Digital Input register This pin can also be configured as the RGATE data separator

diagnostic input via the Mode command (see Section 426)

Disk Change

This pin provides an additional Disk Change signal in PPM Mode when PNFe0 (See

PD4 and Table 7-5 for further information)

DSR12

76 68

Data Set Ready

When low this indicates that the data set or MODEM is ready to establish a

communications link The DSR signal is a MODEM status input whose condition the CPU can test by

reading bit 5 (DSR) of the MODEM Status Register (MSR) for the appropriate channel Bit 5 is the

complement of the DSR signal Bit 1 (DDSR) of the MSR indicates whether the DSR input has

changed state since the previous reading of the MSR

Note

Whenever the DDSR bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled

DSTRB

Data Strobe

This signal is used in EPP mode as data strobe It is active low (See AFD and Tabe 7-5

for further information)

DTR12

71 63

Data Terminal Ready

When low this output indicates to the MODEM or data set that the UART is

ready to establish a communications link The DTR signal can be set to an active low by programming

bit 0 (DTR) of the MODEM Control Register to a high level A Master Reset operation sets this signal

to its inactive (high) state Loop mode operation holds this signal to its inactive state (See CFG4 – 0 for

further information)

ERR

Error

This input is set low by the printer when it has detected an error This pin has a nominal 25 kX

pull-up resistor attached to it (See HDSEL and Table 7-5 for further information)

HCS0

Hard Drive Chip Select 0

This output is active in the AT mode when the hard drive registers from

1F0 – 1F7h are selected if the primary address is used or when 170 – 177h are selected if the

secondary address is used This output is inactive if the IDE interface is disabled via the Configuration

HCS1

Hard Drive Chip Select 1

This output is active in the AT mode when the hard drive registers from

3F6 – 7 are selected if the primary address is used or when 376 – 377 are selected if the secondary

address is used This output is also inactive if the IDE interface is disabled via the Configuration

HDSEL

Head Select

This output determines which side of the FDD is accessed Active selects side 1

inactive selects side 0

Head Select

This pin provides an additional Head Select signal in PPM Mode when PNFe0 (See

ERR and Table 7-5 for further information)

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