TAS5000 datasheet(16/24 Pages) TI

16 / 24 page

2–6

•

Left channel is received when LRCLK is low.

•

Right channel is received when LRCLK is high.

•

SDIN is sampled with the rising edge of SCLK.

2.8.3

MSB Left Justified Serial Interface Format (for 16 bits)

MSB

LSB

MSB

LSB

SCLK

LRCLK = Fs

SDIN

Left Channel

Right Channel

Figure 2–8. MSB Left Justified Serial Interface Format

Note the following characteristics of this protocol.

•

Left channel is received when LRCLK is high.

•

Right channel is received when LRCLK is low.

•

The SDIN data is justified to the leading edge of the LRCLK.

•

SDIN is sampled with the rising edge of SCLK.

2.8.4

DSP Compatible Serial Interface Format (for 16 bits)

SCLK

LRCLK = Fs

SDIN

Left Channel

(MSB = 15)

Right Channel

(MSB = 15)

Figure 2–9. DSP Compatible Serial Interface Format

Note the following characteristics of this protocol.

•

Serial data is sampled with the falling edge of SCLK.

2.9

PWM Outputs

Designed to be used with TAS5100.

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