CDCM1802

CLOCK BUFFER WITH PROGRAMMABLE DIVIDER,

LVPECL I/O + ADDITIONAL LVCMOS OUTPUT

SCAS759 − APRIL 2004

17

POST OFFICE BOX 655303

APPLICATION INFORMATION

enabling a single output stage

If a single output stage becomes enabled:

1. Y0 will either be low or high (undefined).

2. Y0 will be the inverted signal of Y0.

With the first positive clock transition, the undivided output becomes the input clock state. If a divide mode is

used, the divided output states are equal to the actual internal divider. The internal divider does not get a reset

while enabling single output drivers.

High-Z

ENABLE Yx:

IN

Yx:/1

High-Z

Yx:/x

Undefined

Enabled

Disabled

Divider State

Undivided State is Valid After the First

Positive Transition of the Input Clock

Undefined

Figure 17. Signal State After an Output Driver Becomes Enabled While IN = 0

High-Z

ENABLE Yx:

IN

Yx:/1

Undefined

High-Z

Yx:/x

Undefined

Divider State

Enabled

Disabled

Undivided State is Valid After the First

Positive Transition of the Input Clock

Figure 18. Signal State After an Output Driver Becomes Enabled While IN = 1