PEX 8748, PCI Express Gen 3 Switch, 48 Lanes, 12 Ports

© PLX Technology, www.plxtech.com

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10/7/2010, Version 1.0

r1.0a. Additionally, it supports auto-negotiation, lane

reversal, and polarity reversal. Furthermore, the PEX

8748 is tested for Microsoft Vista compliance. All PLX

switches undergo thorough interoperability testing in

PLX’s Interoperability Lab and compliance testing at

the PCI-SIG plug-fest.

performancePAK

™

Exclusive to PLX, performancePAK is a suite of unique

eatures which allows PLX’s

ighest performing Gen 2

being made by downstream

ownstream device requests several long

link

ess ports in

n allowing for higher performance in dual-

w

s opposed to a static buffer

static buffers to each port,

as

nPAK is a debug diagnostics

suite of integrated hardware and software instruments that

elp bring their systems to market faster.

s

ally “see” ingress and egress performance on

h the switch using PLX’s

ws

users can view the receiver

and innovative performance f

Gen 2 switches to be the h

switches in the market today. The performancePAK

features consists of the Read Pacing, Multicast, and

Dynamic Buffer Pool.

Read Pacing

The Read Pacing feature allows users to throttle the

amount of read requests

devices. When a d

reads back-to-back, the Root Complex gets tied up in

serving that downstream port. If that port has a narrow

and is therefore slow in receiving these read packets from

the Root Complex, then other downstream ports may

become starved – thus, impacting performance. The Read

Pacing feature enhances performances by allowing for the

adequate servicing of all downstream devices.

Multicast

The Multicast feature enables the copying of data (packets)

from one ingress port to multiple (up to 11) egr

one transactio

graphics, storage, security, and redundant applications,

among others. Multicast relieves the CPU from having to

conduct multiple redundant transactions, resulting in

higher system performance.

Dynamic Buffer Pool

The PEX 8748 employs a dynamic buffer pool for Flo

Control (FC) management. A

scheme which assigns fixed,

PLX’s dynamic buffer allocation scheme utilizes a

common pool of FC Credits which are shared by other

ports. This shared buffer pool is fully programmable by the

user, so FC credits can be allocated among the ports

needed. Not only does this prevent wasted buffers and

inappropriate buffer assignments, any unallocated buffers

remain in the common buffer pool and can then be used

for faster FC credit updates.

visionPAK

™

Another PLX exclusive, visio

users can use to h

visionPAK features consist of Performance Monitoring,

SerDes Eye Capture, Error Injection, SerDes Loopback,

and more.

Performance Monitoring

The PEX 8748’s real time performance monitoring allow

users to liter

each port as traffic passes throug

Software Development Kit (SDK). The monitoring is

completely passive and therefore has no affect on overall

system performance. Internal counters provide extensive

granularity down to traffic & packet type and even allo

for the filtering of traffic (i.e. count only Memory Writes).

SerDes Eye Capture

Users can evaluate their system’s signal integrity at the

physical layer using the PEX 8748’s SerDes Eye Capture

feature. Using PLX’s SDK,

eye of any lane on the switch. Users can then modify

SerDes settings and see the impact on the receiver eye.

Figure 5 shows a screenshot of the SerDes Eye Capture

feature in the SDK.

Figure 5. SerDes Eye Capture

PCIe Packet Generator

The PEX 87

et

enerator capable of creating programmable PCIe traffic

and capable of saturating a

48 features a full-fledged PCIe Pack

G

running at up to Gen 3 speeds

x16 link. Using PLX’s Software Development Kit

(www.plxtech.com/sdk), designers can create custom

traffic scripts for system bring-up and debug. Fully

integrated into the PEX 8748, the Packet Generator

to be a very convenient on-chip debug tool. Furthermo

the Packet Generator can be used to create PCIe traf

test and debug other devices on the system.

proves

re,

fic to