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ICS854057 Arkusz danych(PDF) 1 Page - Integrated Circuit Systems |
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ICS854057 Arkusz danych(HTML) 1 Page - Integrated Circuit Systems |
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1 / 13 page ![]() 854057AG www.icst.com/products/hiperclocks.html REV. A JULY 18, 2005 1 Integrated Circuit Systems, Inc. ICS854057 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT TERMINATION GENERAL DESCRIPTION The ICS854057 is a 4:1 or 2:1 LVDS Clock Mul- tiplexer which can operate up to 2GHz and is a member of the HiPerClockS™ family of High Per- formance Clock Solutions from ICS. The PCLK, nPCLK pairs can accept most standard differen- tial input levels. Internal termination is provided on each dif- ferential input pair. The ICS854057 operates using a 2.5V sup- ply voltage. The fully differential architecture and low propa- gation delay make it ideal for use in high speed multiplexing applications. The select pins have internal pulldown resistors. Leaving one input unconnected (pulled to logic low by the in- ternal resistor) will transform the device into a 2:1 multiplexer. The SEL1 pin is the most significant bit and the binary num- ber applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0). FEATURES • High speed differential multiplexer.The device can be configured as either a 4:1 or 2:1 multiplexer • Single LVDS output • 4 selectable PCLK, nPCLK inputs with internal termination • PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: >2GHz • Part-to-part skew: 200ps (maximum) • Propagation delay: 800ps (maximum) • Additive phase jitter, RMS: 66fs (typical) • 2.5V operating supply • -40°C to 85°C ambient operating temperature • Available in both, Standard and RoHS/Lead-Free compliant packages HiPerClockS™ ICS 00 01 10 11 BLOCK DIAGRAM PIN ASSIGNMENT VDD PCLK0 VT0 nPCLK0 SEL1 SEL0 PCLK1 VT1 nPCLK1 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD PCLK3 VT3 nPCLK3 Q nQ PCLK2 VT2 nPCLK2 GND ICS854057 20-Lead TSSOP 4.40mm x 6.50mm x 0.925mm body package G Package Top View VT0 PCLK0 nPCLK0 VT1 PCLK1 nPCLK1 VT2 PCLK2 nPCLK2 VT3 PCLK3 nPCLK3 Q nQ 50 50 50 50 50 50 50 50 SEL1 SEL0 Pulldown Pulldown |
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