CY28329
Document #: 38-07040 Rev. *E
Page 5 of 17
Data Byte 1:
Bit
Pin#
Name
Description
Type
Power On
Default
Bit 7
–
CPU Mult0 Value
R
HW
Bit 6
53, 54
CPU3
CPU3#
CPU3 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 5
–
–
Reserved, set = 0
R/W
0
Bit 4
–
–
Reserved, set = 0
R/W
0
Bit 3
–
–
Reserved, set = 0
R/W
0
Bit 2
44, 45
CPU2
CPU2#
CPU2 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 1
48, 49
CPU1
CPU1#
CPU1Output Enable
1 = Enabled; 0= Disabled
R/W
1
Bit 0
51, 52
CPU0
CPU0#
CPU0 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Data Byte 2:
Bit
Pin#
Name
Pin Description
Type
Power On
Default
Bit 7
–
–
Reserved, set = 0
R
0
Bit 6
18
PCI6
PCI6 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 5
17
PCI5
PCI5 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 4
16
PCI4
PCI4 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 3
13
PCI3
PCI3 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 2
12
PCI2
PCI2 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 1
11
PCI1
PCI1 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Bit 0
10
PCI0
PCI0 Output Enable
1 = Enabled; 0 = Disabled
R/W
1
Data Byte 3:
Bit
Pin#
Name
Pin Description
Type
Power On
Default
Bit 7
38
DOT
DOT 48 MHz Output Enable, 1 = enabled, 0 = disabled
R/W
1
Bit 6
39
USB
USB 48 MHz Output Enable, 1 = enabled, 0 = disabled
R/W
1
Bit 5
7
PCI_F2
Allow control of PCI_F2 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
R/W
0
Bit 4
6
PCI_F1
Allow control of PCI_F1 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
R/W
0
Bit 3
5
PCI_F0
Allow control of PCI_F0 with assertion of PCI_STOP#
0 = Free running; 1 = Stopped with PCI_STOP#
R/W
0
Bit 2
7
PCI_F2
PCI_F2 Output Enable, 1 = enabled, 0 = disabled
R/W
1
Bit 1
6
PCI_F1
PCI_F1Output Enable, 1 = enabled, 0 = disabled
R/W
1
Bit 0
5
PCI_F0
PCI_F0 Output Enable, 1 = enabled, 0 = disabled
R/W
1
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