IC-HTG datasheet(21/40 Pages) ICHAUS

21 / 40 page

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iC-HTG

POWER CW LASER DIODE DRIVER

Rev A1, Page 21/40

10-BIT LINEAR A/D CONVERTER

A 10-bit linear A/D converter is available for a variety

of voltages that can be measured with different resolu-

tions:

• V(VDD) up to 5.5 V with 8.6 mV resolution

• V(VBL) up to 30 V with 32.3 mV resolution

• V(VB) up to 30 V with 32.3 mV resolution

• V(MDL) internal voltage up to 1.1 V with 1.075 mV

resolution

• V(MC) internal voltage up to 1.1 V with 1.075 mV res-

olution

• V(VRN) up to 30 V with 32.3 mV resolution

• V(VRP) up to 30 V with 32.3 mV resolution

• V(ANIN) up to 1.1 V with 1.075 mV resolution

As described in block diagram on Page 1, the voltages

V(VDD), V(VBL), V(VB), V(VRN), V(VRP) and V(ANIN)

are th PIN Voltage directly. V(MC) is proportional to

the laser current value and is the voltage difference be-

tween pins MCH and MCL. (V(MC)=V(MCH)-V(MCL)).

The voltage V(MDL) is proportional to the optical laser

power (monitor current) and the value is the absolute

value of the difference between the pins MD and MR

(V(MDL)=|V(MD)-V(MR)|).

The register ADCC(2:0) select the signal measured with

the 10-bit A/D converter.

ADCC(2:0)

Addr. 0x10; bit 7:5

R/W 000

000

ADC sourced by V(VDD) ÷ 8 (3V .. 5.5V)

001

ADC sourced by V(VBL) ÷ 30 (3V .. 24V)

010

ADC sourced by V(VB) ÷ 30 (3V .. 24V)

011

ADC sourced by V(MDL) (0V .. 1.1V)

100

ADC sourced by V(MC) (0V .. 1.1V)

101

ADC sourced by V(VRN) ÷ 30 (0V .. 24V)

110

ADC sourced by V(VRP) ÷ 30 (0V .. 24V)

111

ADC sourced by V(ANIN) (0V .. 1.1V)

Table 30: ADC source selection

When enabled, the A/D converter continuously acquires

the signal selected by ADCC register. The conversion

time is 140 µs. Changing the source requires 500 µs

settling time.

The converter does not provide an end of conversion

(EOC) bit, the ADC(9:0) register always contains the

value of the last valid conversion.

As the A/D converter has a resolution of 10 bits, the

results are split into two, one byte wide, separate reg-

isters; ADCh contains ADC MSBs values while ADCl

stores the LSBs. A consecutive read of both registers

(lower and upper part) should be carried out in order

to prevent an undesired change in the measured value

between two read commands.

ADC(9:8)

Addr. 0x03; bit 1:0

ADC(7:0)

Addr. 0x04; bit 7:0

0x000

ADC minimum value

...

0x3FF

ADC maximum value

Table 31: ADC

The voltage corresponding to the measured digital

value can be directly obtained using the following for-

mula:

V(VBL, VB, VRP, VRN) = 30 ∗ VFS

1024 ∗ ADCx

V(VDD) = 8 ∗ VFS

1024 ∗ ADCx

V(MDL, MC, ANIN) = VFS

1024 ∗ ADCx

VFS is the full scale voltage of the A/D converter (cf.

Electrical Characteristics No. 706) typically 1.1 V. For

a more precise measurement, the A/D converter can

be calibrated by measuring a known VB voltage and

calculating the VFS.

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