LT6220/LT6221/LT6222

17

sn622012 622012fs

PACKAGE DESCRIPTIO

DD Package

8-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698)

PACKAGE DESCRIPTIO

and the output of the lower path is:

Note that the input common mode voltage does not appear

in the output as either a common mode or a difference

output terms, and with the same polarity, so it sets up the

appears fully at both outputs with opposite polarity, giving

rise to the effective differential gain of 2. Calculations show

that using 1% resistors gives worst-case input common

mode feedthrough better than –31dB, whether looking at

the output common mode or difference mode. Consider-

ing the 6dB of gain, worst-case common mode rejection

ratio is 37dB. (Remember this is assuming 1% resistors.

Of course, this can be improved with more precise resis-

tors.) Results achieved on the bench with typical 1%

resistors showed 67dB of CMRR at low frequency and

40dB CMRR at 1MHz. Gains other than 2 can be achieved

by setting R3 = α • (R1||R2), R5 = α• R4 and R7 = α • R6

where gain = α.

3.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

0.38 ± 0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ± 0.10

(2 SIDES)

0.75 ±0.05

R = 0.115

TYP

2.38 ±0.10

(2 SIDES)

1

4

8

5

PIN 1

TOP MARK

(NOTE 6)

0.200 REF

0.00 – 0.05

(DD8) DFN 1203

0.25 ± 0.05

2.38 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 ±0.05

(2 SIDES)

2.15 ±0.05

0.50

BSC

0.675 ±0.05

3.5 ±0.05

PACKAGE

OUTLINE

0.25 ± 0.05

0.50 BSC