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CS42516 Arkusz danych(PDF) 79 Page - Cirrus Logic |
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CS42516 Arkusz danych(HTML) 79 Page - Cirrus Logic |
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79 / 90 page ![]() DS583F1 79 CS42516 10.1.2 Jitter Attenuation Figures 28 and 29 show the jitter-attenuation characteristics for the 32-192 kHz sample rate range when used with the external PLL component values and locking modes as specified in Table 21. The AES3 and IEC60958-4 specifications do not have allowances for locking to sample rates less than 32 kHz or for locking to the SAI_LRCK input. These specifications state a maximum of 2 dB jitter gain or peaking. Figure 28. Jitter-Attenuation Characteristics of PLL - Configurations 1 & 2 Figure 29. Jitter-Attenuation Characteristics of PLL - Configuration 3 |
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