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CS42526 Arkusz danych(PDF) 13 Page - Cirrus Logic

Numer części CS42526
Szczegółowy opis  114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver
PDF  90 Pages
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Producent  CIRRUS [Cirrus Logic]
Strona internetowa  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS42526 Arkusz danych(HTML) 13 Page - Cirrus Logic

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CS42526
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT (For CQZ, T
A
= -10 to +70° C; For DQZ, TA = -40 to +85° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs:
Logic 0 = DGND, Logic 1 = VLC, CL =30pF)
Notes: 16. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
17. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
18.
for Single-Speed Mode,
for Double-Speed Mode,
for Quad-Speed Mode
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
Setup Time for Repeated Start Condition
tsust
4.7
-
µs
SDA Hold Time from SCL Falling
(Note 16)
thdd
0-
µs
SDA Setup time to SCL Rising
tsud
250
-
ns
Rise Time of SCL and SDA
trc
-1
µs
Fall Time SCL and SDA
tfc
-300
ns
Setup Time for Stop Condition
tsusp
4.7
-
µs
Acknowledge Delay from SCL Falling
(Note 17)
tack
-
(Note 18)
ns
15
256
Fs
×
---------------------
15
128
Fs
×
---------------------
15
64
Fs
×
------------------
t
buf
t
hd s t
t
lo w
t
hd d
t
hig h
t
su d
Sto p
S t a r t
SD A
SC L
t
irs
RS T
t
hdst
t
rc
t
fc
t sust
t susp
St ar t
Sto p
R e pe at e d
t
rd
t
fd
t
ac k
Figure 3. Control Port Timing - I2C Format



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