CF52012 datasheet(31/48 Pages) INTEL

31 / 48 page

Figure 7.

4BYTEADDREX Timing Diagram

Operation Code (E9h)

3 4 5 6 7

nCS

DCLK

DATA0

Related Information

Write Enable Operation (06h) on page 31

1.7.2. Write Enable Operation (06h)

When you enable the write enable operation, the write enable latch bit is set to 1 in

the status register. You must execute this operation before the write bytes, write

status, erase bulk, erase sector, extended dual input fast write bytes, extended quad

input fast write bytes, 4BYTEADDREN, and 4BYTEADDREX operations.

Figure 8.

Write Enable Operation Timing Diagram

nCS

DCLK

DATA0

DATA[3:1]

Operation Code (06h)

High Impedance

1.7.3. Write Disable Operation (04h)

The write disable operation resets the write enable latch bit in the status register. To

prevent the memory from being written unintentionally, the write enable latch bit is

automatically reset when implementing the write disable operation, and under the

following conditions:

•

Power up

•

Write bytes operation completion

•

Write status operation completion

•

Erase bulk operation completion

•

Erase sector operation completion

•

Extended dual input fast write bytes operation completion

•

Extended quad input fast write bytes operation completion

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 | 2018.06.01

Quad-Serial Configuration (EPCQ) Devices Datasheet

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