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STC89LE52RC Arkusz danych(PDF) 36 Page - STCmicro Technology Co,.Ltd

Numer części STC89LE52RC
Szczegółowy opis  Enhanced 80C51 Central Processing Unit ,6T or 12T per machine cycle
PDF  165 Pages
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Producent  STC [STCmicro Technology Co,.Ltd]
Strona internetowa  http://www.stcmicro.com/
Logo STC - STCmicro Technology Co,.Ltd

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Register-Specific Instruction
Some instructions are specific to a certain register. For example, some instructions always operate on the
accumulator or data pointer,etc. No address byte is needed for such instructions. The opcode itself does it.
Immediate Constant(IMM)
The value of a constant can follow the opcode in the program memory.
Index Addressing
Only program memory can be accessed with indexed addressing and it can only be read. This addressing mode is
intended for reading look-up tables in program memory. A 16-bit base register(either DPTR or PC) points to the
base
of the table, and the accumulator is set up with the table entry number. Another type of indexed
addressing is used in the conditional jump instruction.
In conditional jump, the destination address is computed as the sum of the base pointer and the
accumulator.
5.2 Addressing Modes
Addressing modes are an integral part of each computer's instruction set. They allow specifyng the source or
destination of data in different ways, depending on the programming situation. There eight modes available:
Register
Direct
Indirect
Immediate
Relative
Absolute
Long
Indexed
Direct Addressing(DIR)
In direct addressing the operand is specified by an 8-bit address field in the instruction. Only internal data RAM
and SFRs can be direct addressed.
Indirect Addressing(IND)
In indirect addressing the instruction specified a register which contains the address of the operand. Both internal
and external RAM can be indirectly addressed.
The address register for 8-bit addresses can be R0 or R1 of the selected bank, or the Stack Pointer.
The address register for 16-bit addresses can only be the 16-bit data pointer register – DPTR.
Register Instruction(REG)
The register banks, containing registers R0 through R7, can be accessed by certain instructions which carry a 3-bit
register specification within the opcode of the instruction. Instructions that access the registers this way are code
efficient because this mode eliminates the need of an extra address byte. When such instruction is executed, one
of the eight registers in the selected bank is accessed.
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