PD780 datasheet(2/24 Pages) NEC

2 / 24 page

/APD780

Pin Identification

No.

Symbol

Function

1-5.

A o-

A 15

ree-st

a te

address bus

30-

(output)

Clock input

7-10.

Do-D7

ree-st

a te. 110

da ta

bus

12-15

+5 V

Powe

supply

INT

Inte

rrupt

request input

NMI

Non-m

ask

a ble inte

rrupt input

HA LT

Ha lt st

a te input

MREQ

Memo

r y request output

10RQ

110 request

output

a d output

Wr ite output

SA K

Bus

acknowledge output

WAIT

Wa it st

a te input

SRQ

Bus

requestinput

RE SE T

Reset

input

Ma ch ine cycle

Refresh

output

Ground

Pin Functions

Ao-A15 (Address Bus)

16-bit, three-state output address bus. During refresh

operations, lines Ao-A6 output the external memory

address.

00-07 (Data Bus)

8-bit, three-state I/O data bus.

NMI (Non-Maskable Interrupt)

This active low input line is used for non-maskable

interrupts. A non-maskable interrupt is always

acknowledged at the end of the current instruction,

regardless of whether the interrupt enable flip flop has

been turned on, except when the BUSRQ signal is

asserted. Because of the higher priority of the BUSRQ

signal, it is acknowledged before the NMI signal.

When NMI is acknowledged, program execution

automatically restarts from location 0066H.

4-4

NEe

INT (Interrupt Request)

This active low input line is used for interrupt requests

by external I/O devices. Interrupts are serviced upon

completion of the current instruction if the interrupt

enable flip flop has been turned on by the software.

There are three interrupt response modes: the mode

o response is equivalent to an8080 interrupt response;

mode 1 uses location 0038H as a restart address; and

mode 2 is a simple vectoring to an interrupt service

routine that can be located anywhere in memory.

BUSRQ (Bus Request)

This active low input signal is used to place the data

bus, address bus, and a" three-state bus control

signals (WR, RD, 10RQ, and MREQ) in a high

impedance state to allow a requesting device to

assume bus control. The BUSRQ signal has a higher

priority than the NMI signal and is always honored at

the end of the current machine cycle.

Excessive DMA operations resulting in long periods

in which BUSRQ is asserted can impair the CPU's

ability to adequately refresh the dynamic RAMs. Also,

BUSRQ does not have an internal pull-up resistor. For

input signals to this pin in a wire-OR'ed configuration,

an external pull-up resistor should be used.

BUSAK (Bus Acknowledge)

This active low output line is used to inform the device

requesting bus control that the data bus, address bus,

and a" three-state bus controls (WR, RD, 10RQ, and

MREQ) are in a high-impedance state and the re

questing device can now assume control.

WR (Write)

This three-state active low output is used to strobe

data from the data bus to external memory or I/O

devices. WR is asserted to indicate the data bus holds

valid dlita. This line is three-stated during halt or reset

conditions.

10RQ (1/0 Request)

This three-state active low output is used to indicate

the lower half of the address bus holds a valid address

for an I/O read or write. During interrupt acknowledge

cycles, 10RQ and Ml are asserted together to indicate

that a vector address can be sent to the data bus.

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