CS42406 datasheet(27/50 Pages) CIRRUS

27 / 50 page

CS42406

SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE Inputs: Logic

0 = GND, Logic 1 = VLC

Notes: 19. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

20. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

21.

for Single-Speed Mode,

for Double-Speed Mode,

for Quad-Speed Mode.

Parameter

Symbol

Min

Max

Unit

I²C Mode

SCL Clock Frequency

fscl

100

kHz

DAC_RST Rising Edge to Start

tirs

500

Bus Free Time Between Transmissions

tbuf

4.7

µs

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

µs

Clock Low time

tlow

4.7

µs

Clock High Time

thigh

4.0

µs

Setup Time for Repeated Start Condition

tsust

4.7

µs

SDA Hold Time from SCL Falling

(Note 19)

thdd

µs

SDA Setup time to SCL Rising

tsud

250

Rise Time of SCL and SDA

trc, trc

-1

µs

Fall Time SCL and SDA

tfc, tfc

300

Setup Time for Stop Condition

tsusp

4.7

µs

Acknowledge Delay from SCL Falling

(Note 20)

tack

(Note 21)

256

-----------------------

128

-----------------------

--------------------

buf

hdst

low

hdd

high

sud

Stop

Start

SDA

SCL

irs

hdst

t sust

t susp

Start

Stop

Repeated

ack

DAC_RST

Figure 31. Control Port Timing - I²C Mode

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