PIC12F635ESLASHP datasheet(49/196 Pages) MICROCHIP

49 / 196 page

Preliminary

DS41232B-page 47

PIC12F635/PIC16F636/639

4.2.4.5

RA4/T1G/OSC2/CLKOUT

Figure 4-5 shows the diagram for this pin. The RA4 pin

is configurable to function as one of the following:

• a general purpose I/O

• a TMR1 gate input

• a crystal/resonator connection

• a clock output

FIGURE 4-5:

BLOCK DIAGRAM OF RA4

4.2.4.6

RA5/T1CKI/OSC1/CLKIN

Figure 4-6 shows the diagram for this pin. The RA5 pin

is configurable to function as one of the following:

• a general purpose I/O

•a TMR1 clock input

• a crystal/resonator connection

• a clock input

FIGURE 4-6:

BLOCK DIAGRAM OF RA5

I/O pin

VDD

VSS

XTAL

PORTA

TRISA

IOCA

Fosc/4

Oscillator

Circuit

OSC1

CLKOUT

Enable

RD PORTA

T1G To Timer1

INTOSC/

RC/EC(2)

CLKOUT

Enable

Note

Oscillator modes are XT, HS, LP, LPTMR1 and

CLKOUT Enable.

With CLKOUT option.

Interrupt-on-

change

Data Bus

WPUDA

RAPU

WDA

VDD

Weak

VSS

CLK(1) Modes

I/O pin

VDD

VSS

PORTA

TRISA

IOCA

T1G To Timer1

INTOSC

Mode

RD PORTA

OSC2

(2)

Note

Oscillator modes are XT, HS, LP and LPTMR1.

When using Timer1 with LP oscillator, the

Schmitt Trigger is bypassed.

Interrupt-on-

change

Oscillator

Circuit

Data Bus

WPUDA

RAPU

WDA

VDD

Weak

VSS

CLK(1) Modes

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