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MSHFS Arkusz danych(PDF) 4 Page - Mixed Signal Integration |
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MSHFS Arkusz danych(HTML) 4 Page - Mixed Signal Integration |
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4 / 5 page ![]() Selectable High Frequency LP/BPFilter Data Sheet 7/2016 Block Diagram________________ SCF Section One 4 Input MUX Filter and Clock Select (TYPE, FSEL, Fo) SCF Section Buffer Adjustable Gain IN1 IN2 IN3 IN4 G Out o S1 S2 Input Selection The input is selected using the Input Select Pins S1 and S2. S2 S1 Input 0 0 1 0 1 2 1 0 3 1 1 4 Digital Levels All the clock and control pins (except FSEL, CLK and G) are referenced between GND and VDD. In single supply applications, the digital levels should be CMOS levels from VSS to VDD. In dual supply systems, the digital levels should be CMOS levels from GND to VDD. Absolute Maximum Ratings Power Supply Voltage +6V Storage Temperature -60 to +150 C Operating Temperature -40 to +85 C Part Number Package Operating Temperature -40 - 85 C -40 - 85 C -40 - 85 C -40 - 85 C -40 - 85 C -40 - 85 C -40 - 85 C -40 - 85 C -40 - 85 C -40 - 85 C -40 - 85 C -40 - 85 C MSHFS1P 8 Pin Dip MSHFS2P 16 Pin Dip MSHFS3P MSHFS4P 16 Pin Dip MSHFS5P 8 Pin Dip MSHFS6P 8 Pin Dip MSHFS1S MSHFS2S 16 Pin SOIC MSHFS3S 8 Pin SOIC MSHFS4S 16 Pin SOIC MSHFS5S 8 Pin SOIC MSHFS6S 8 Pin SOIC 8 Pin Dip 8 Pin SOIC © 2000-2016 Mixed Signal Integration 4 To order a RoHS compliant part, add “-RoHS” to the end of a part number above. |
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