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RM3182S Arkusz danych(PDF) 7 Page - List of Unclassifed Manufacturers

Numer części RM3182S
Szczegółowy opis  ARINC 429 Differential Line Driver
PDF  8 Pages
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Producent  ETC1 [List of Unclassifed Manufacturers]
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RM3182S Arkusz danych(HTML) 7 Page - List of Unclassifed Manufacturers

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PRODUCT SPECIFICATION
RM3182
7
Mechanical Dimensions (continued)
28 Terminal Leadless Chip Carrier (LCC)
DETAIL "A"
B1
A1
A
D2
(j) x 45
°
L1
L2
DETAIL "A"
E
LID
See Note 1
Index Corner
D
(h) x 45
°
3 PLCS
4
B3
L3
PLANE 2
PLANE 1
A
.060
.100
1.52
2.54
Symbol
Inches
Min.
Max.
Min.
Max.
Millimeters
Notes
A1
.050
.088
1.27
2.24
B1
.022
.56
.028
.71
B3
.006
.022
.15
.56
D1/E1
D2/E2
e
.050 BSC
1.27 BSC
h
.040 REF
1.02 REF
.020 REF
.51 REF
7
7
28
28
.300 BSC
7.62 BSC
.150 BSC
3.81 BSC
j
3, 6
3, 6
2
2, 5
4
4
5
L1
L2
ND/NE
N
L3
.015
.38
.003
.08
D/E
.442
.460
11.23
11.68
.045
.055
1.14
1.40
.075
.095
1.91
2.41
Notes:
1.
2.
3.
4.
5.
6.
The index feature for terminal 1 identification, optical orientation or
handling purposes, shall be within the shaded index areas shown on
planes 1 and 2. Plane 1 terminal 1 identification may be an extension
of the length of the metallized terminal which shall not be wider than
the B1 dimension.
Unless otherwise specified, a minimum clearance of .015 inch
(0.38mm) shall be maintained between all metallized features
(e.g., lid, castellations, terminals, thermal pads, etc.).
Dimension "A" controls the overall package thickness. The maximum
"A" dimension is the package height before being solder dipped.
The corner shape (square, notch, radius, etc.) may vary at the
manufacturer's option, from that shown on the drawing. The index
corner shall be clearly unique.
Dimension "B3" minimum and "L3" minimum and the appropriately
derived castellation length define an unobstructed three dimensional
space traversing all of the ceramic layers in which a castellation was
designed. Dimension "B3" maximum and "L3" maximum define the
maximum width and depth of the castellation at any point on its
surface. Measurement of these dimensions may be made prior to
solder dripping.
Chip carriers shall be constructed of a minimum of two ceramic layers.
e
D1



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