SC284P datasheet(15/22 Pages) SEMTECH

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SC284P

Applications Information (continued)

Power Save Mode Operation

WhentheloadcurrentdecreasesbelowthePSAVEthreshold,

PWM switching stops and the device automatically enters

PSAVE mode.This threshold varies depending upon the in-

putvoltageandtheoutputvoltagesetting,optimizingeffi-

ciencyforallpossibleloadcurrentsinPWMorPSAVEmode.

While in PSAVE mode, output voltage regulation is

controlled by a series of switching bursts. During a

burst, the inductor current is limited to a peak value

which controls the on-time of the PMOS switch. Af-

ter reaching this peak, the PMOS switch is disabled

and the inductor current decreases to near 0mA.

Switching bursts continue until the output voltage climbs

to VOUT +2.5% or until the PSAVE current limit is reached.

Switching is then stopped to eliminate switching losses,

enhancing overall efficiency. Switching resumes when

the output voltage reaches the lower threshold of VOUT

and continues until the upper threshold again is reached.

Note that the output voltage is regulated hysteretically

while in PSAVE mode between VOUT and VOUT + 2.5%.

The period and duty cycle while in PSAVE mode are

solely determined by VIN and VOUT until PWM mode

resumes. This can result in the switching frequency be-

ing much lower than the PWM mode frequency. If the

output load current increases enough to cause VOUT to

decrease below the PSAVE exit threshold (VOUT-4%),

the device automatically exits PSAVE and operates in

continuous PWM mode. Note that the PSAVE high and

low threshold levels are both set at or above

VOUT to minimize undershoot when the SC284P

exits PSAVE mode and returns to PWM mode.

Figure 2 - Transitions Between PWM and PSAVE Modes

Power Good

PGOOD is an open-drain output.When the output volt-

age drops below nominal voltage, the PGOOD pin is

pulled low after a 20μs delay. During start-up, PGOOD

will be asserted .7ms (typ.) after the output voltage

reaches 90% of the final regulation voltage.Over volt-

age, fold-back current limit and thermal shutdown will

force PGOOD low after a 20μs delay. When recovering

from a fault, PGOOD will be asserted .7ms (typ.) af-

ter Vout reaches 90% of the final regulation voltage.

Maximum Power Dissipation

Each channel of SC284P has its own Θ

JA of 40°C/W when

only one channel is in operation. Since both channels are

within the same package, please make sure to use both

channelsforpowercalculations. Toguaranteeanoperating

junction temperature of less than 25°C, Figure 3 shows

the maximum allowable power loss for each channel. The

curve is based upon the junction temperature of either

channel reaching a maximum of 25°C. Each channel of

SC284P can support up to 2A load current.

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

2.2

2.4

2.6

2.8

0 0.2 0.4 0.6 0.8 1

1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8

Loss of Channel A (W)

TA = 25°C

TA = 55°C

TA = 85°C

Figure 3 — Maximum allowable loss for each channel

for a maximum junction temperature of 125°C

VOUT - 4%

VOUT

V OUT +2.5%

Load

(IOUT)

BU R ST

O FF

VLX

Tim e

PW M M ode at

M edium/H igh

Load

PSAVE M ode at

Light Load

PW M M ode at

M edium /H igh

Load

PSAVE

EXIT

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