AM186ED-20KCSLASHW datasheet(26/88 Pages) AMD

26 / 88 page

Am186ED/EDLV Microcontrollers

PRELI M INARY

F T

the midrange memory block are programmable. MCS2

is configured for 8-bit or 16-bit bus size via the auxiliary

configuration register.

MCS2 is three-stated and held resistively High during a

bus hold condition. In addition, it has a weak internal

pullup resistor that is active during reset.

If MCS0 is programmed to be active for the entire

middle chip-select range, then this signal is available

as a PIO or a DRAM control. If this pin is not

programmed as a PIO or DRAM control and if MCS0 is

programmed for the whole middle chip-select range,

this signal operates normally.

LCAS—When either bank of DRAM is activated, the

LCAS functionality is enabled. The LCAS activates

when the DRAM access is for the AD7–AD0 byte.

LCAS also activates at the start of a DRAM refresh

access.

LCAS is three-stated and held resistively High during a

bus hold condition. In addition, LCAS has a weak

internal pullup resistor that is active during reset.

MCS3/RAS1/PIO25

Midrange Memory Chip Select 3

(output, synchronous, internal pullup)

Row Address Strobe 1 (output, synchronous)

MCS3—This pin indicates to the system that a memory

access is in progress to the fourth region of the

midrange memory block. The base address and size of

the mid-range memory block are programmable.

MCS3 is configured for 8-bit or 16-bit bus size by the

auxiliary configuration register.

MCS3 is three-stated and held resistively High during a

bus hold condition. In addition, this pin has a weak

internal pullup resistor that is active during reset.

If MCS0 is programmed for the entire middle chip-

select range, then this signal is available as a PIO or a

DRAM control. If MCS3 is not programmed as a PIO or

DRAM control and if MCS0 is programmed for the

entire middle chip-select range, this signal operates

normally.

RAS1—This pin is the row address strobe for the upper

D R AM blo ck. T h e se le ctio n of RAS 1 o r U C S

functionality, along with their configurations, are set

using the UMCS register. When RAS1 is activated, the

code activating RAS1 must not reside in the UCS

memory block. When RAS1 is activated, UCS is

automatically deactivated and remains negated.

RAS1 is three-stated and held resistively High during a

bus hold condition. In addition, RAS1 has a weak

internal pullup resistor that is active during reset.

NMI

Nonmaskable Interrupt (input, synchronous,

edge-sensitive)

This pin indicates to the microcontroller that an

interrupt request has occurred. The NMI signal is the

highest priority hardware interrupt and, unlike the

I N T 6–I NT 0 pin s , cann ot be m a sked. The

microcontroller always transfers program execution to

the location specified by the nonmaskable interrupt

vector in the microcontroller interrupt vector table when

NMI is asserted.

Although NMI is the highest priority interrupt source, it

does not participate in the priority resolution process of

the maskable interrupts. There is no bit associated with

NMI in the interrupt in-service or interrupt request

registers. This means that a new NMI request can

interrupt an executing NMI interrupt service routine. As

with all hardware interrupts, the IF (interrupt flag) is

cleared when the processor takes the interrupt,

disabling the maskable interrupt sources. However, if

maskable interrupts are re-enabled by software in the

NMI interrupt service routine, via the STI instruction for

example, the fact that an NMI is currently in service

does not have any effect on the priority resolution of

maskable interrupt requests. For this reason, it is

strongly advised that the interrupt service routine for

NMI should not enable the maskable interrupts.

An NMI transition from Low to High is latched and

synchronized internally, and it initiates the interrupt at

the next instruction boundary. To guarantee that the

interrupt is recognized, the NMI pin must be asserted

for at least one CLKOUTA period.

PCS1/PIO17, PCS0/PIO16

Peripheral Chip Selects (output, synchronous)

These pins indicate to the system that a memory

access is in progress to the corresponding region of the

peripheral memory block (either I/O or memory

address space). The base address of the peripheral

memory block is programmable.

The PCS chip selects can overlap either block of

DRAM. The PCS chip selects must have the same or

greater number of wait states as the bank of DRAM

they overlap. The PCS signals take precedence over

DRAM accesses when DRAM and memory-mapped

peripherals overlap.

PCS1–PCS0 are three-stated and held resistively High

during a bus hold condition. In addition, PCS1–PCS0

each have a weak internal pullup resistor that is active

during reset.

Unlike the UCS and LCS chip selects, the PCS outputs

assert with the multiplexed AD address bus. Note also

that each peripheral chip select asserts over a 256-

byte address range, which is twice the address range

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