ADF7012 datasheet(16/28 Pages) AD

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ADF7012

Rev. 0 | Page 16 of 28

OUTPUT DIVIDER

An output divider is a programmable divider following the

VCO in the PLL loop. It is useful when using the ADF7012 to

generate frequencies of < 500 MHz.

PFD

OUTPUT

DIVIDER

LOOP

FILTER

REFERENCE

DIVIDER

÷N

÷1/2/4/8

VCO

Figure 35. Output Divider Location in PLL.

The output divider may be used to reduce feedthrough of the

VCO by amplifying only the VCO/2 component, restricting the

VCO feedthrough to leakage.

Because the divider is in loop, the N register values should be

set up according to the usual formula. However, the VCO gain

(KV) should be scaled according to the divider setting, as shown

in the following example.

Fout = 433 MHz, Fvco = 866 MHz, KV @ 868 MHz =

60 MHz/V

Therefore, KV for loop filter design = 30 MHz/V.

The divider value is set in the R register.

Table 5.

OD1

OD2

Divider Status

Divider off

Divide by 2

Divide by 4

Divide by 8

MUXOUT MODES

The MUXOUT pin allows the user access to various internal

signals in the transmitter, and provides information on the

PLL lock status, the regulator, and the battery voltage. The

MUXOUT is accessed by programming Bits M1 to M4 in the

function register and observing the signal at the MUXOUT pin.

Battery Voltage Read back

By setting MUXOUT to 1010 to 1101, the battery voltage can be

estimated. The battery measuring circuit features a voltage

divider and a comparator where the divided-down supply

voltage is compared to the regulator voltage.

Table 6.

MUXOUT

MUXOUT High

MUXOUT Low

1010

DVDD > 3.25 V

DVDD < 3.25 V

1011

DVDD > 3.0 V

DVDD < 3.0 V

1100

DVDD > 2.75 V

DVDD < 2.75 V

1101

DVDD > 2.35 V

DVDD < 2.35 V

The accuracy of the measurement is limited by the accuracy of

the regulator voltage and also the internal resistor tolerances.

Regulator Ready

The regulator has a power-up time, dependant on process and

the external capacitor. The regulator ready signal indicates that

the regulator is fully powered, and that the serial interface is

active. This is the default setting on power-up at MUXOUT.

Digital Lock Detect

Digital lock detect indicates that the status of the PLL loop.

The PLL loop takes time to settle on power-up and when the

frequency of the loop is changed by changing the N value.

When lock detect is high, the PFD has counted a number of

consecutive cycles where the phase error is < 15 ns. The lock

detect precision bit in the function register determines whether

this is 3 cycles (LDP = 0), or 5 cycles (LDP=1). It is recom-

mended that LDP be set to 1. The lock detect is not completely

accurate and goes high before the output has settled to exactly

the correct frequency. In general, add 50% to the indicated

lock time to obtain lock time to within 1 kHz. The lock detect

signal can be used to decide when the power amplifier (PA)

should be enabled.

R Divider

MUXOUT provides the output of the R divider. This is a

narrow pulsed digital signal at frequency FPFD. This signal may

be used to check the operation of the crystal circuit and the R

divider. R divider/2 is a buffered version of this signal at FPFD/2.

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