ST24E64 datasheet(11/16 Pages) STMICROELECTRONICS

Numer części	ST24E64

Szczegółowy opis	SERIAL EXTENDED ADDRESSING COMPATIBLE WITH I2C BUS 64K (8K x 8) EEPROM

PDF	16 Pages

Scroll/Zoom	100%

Producent	STMICROELECTRONICS [STMicroelectronics]

Strona internetowa	http://www.st.com

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11 / 16 page

BYTE WRITE

DEV SEL

BYTE ADDR

DATA IN

PAGE WRITE

DEV SEL

BYTE ADDR

DATA IN 1

DATA IN 2

AI01120

PAGE WRITE

(cont’d)

WC (cont’d)

DATA IN N

ACK

NO ACK

R/W

ACK

NO ACK

R/W

NO ACK

Figure 9. Write Modes Sequence with Write Control = 1

sequence. To terminate the stream of bytes, the

master must NOT acknowledge the last byte out-

put, but MUST generate a STOP condition. The

output data is from consecutive byte addresses,

with the internal byte address counter automat-

ically incremented after each byte output. After a

count of the last memory address, the address

counter will ’roll-over’ and the memory will continue

to output data.

Acknowledge in Read Mode. In all read modes

the ST24/25E64 wait for an acknowledge during

the 9th bit time. If the master does not pull the SDA

line low during this time, the ST24/25E64 terminate

the data transfer and switch to a standby state.

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ST24E64, ST25E64

ST24E64 Arkusz danych(PDF) 11 Page - STMicroelectronics