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STR720 Arkusz danych(PDF) 187 Page - STMicroelectronics |
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STR720 Arkusz danych(HTML) 187 Page - STMicroelectronics |
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187 / 401 page ![]() STR720 - BUFFERED SPI (BSPI) 187/401 Figure 23. BSPI Block Diagram 17.3.1 BSPI Pin Description The BSPI is a four wire, bi-directional bus. The data path is determined by the mode of operation selected. A master and a slave mode are provided together with the associated pad control signals to control pad direction. These pins are described in Table 46 on page 187. Table 46. BSPI pins Pin Name Description SCK The bit clock for all data transfers. When the BSPI is a master the SCK is output from the chip. When configured as a slave the SCK is input from the external source. MISO Master Input/Slave Output serial data line. MOSI Master Output/Slave Input serial data line. SS Slave Select. The SS input pin is used to select a slave device. Must be pulled low after the SCK is stable and held low for the duration of the data transfer. The SS on the master must be deasserted high.This signal can be masked when in master mode-see register description of CSR Reg3 bit 0 16 WORD RECEIVE (16 bits) MOSI SCK MISO SS SHIFT REGISTER FIFO S M M S PIN CONTROL LOGIC S M BSPI CONTROL LOGIC BSPCLK BSPCSR1 CLK DATA BUS 16 16 16 16 16 16 BSPCSR2 16 16 WORD TRANSMIT (16 bits) FIFO BSPCSR3 16 DMA INTERFACE 1 |
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