ST72311 datasheet(37/94 Pages) STMICROELECTRONICS

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ST72311

16-BIT TIMER (Cont’d)

4.3.3.3 Input Capture

In this section, the index, i, may be 1 or 2.

The two input capture 16-bit registers (IC1R and

IC2R) are used to latch the value of the free run-

ning counter after a transition detected by the

ICAPi pin (see figure 5).

ICi Rregister is a read-only register.

The active transition is software programmable

through the IEDGi bit of the Control Register (CRi).

Timing resolution is one count of the free running

counter: (

fCPU/(CC1.CC0)).

Procedure

To use the input capture function select the follow-

ing in the CR2 register:

– Select the timer clock (CC1-CC0) (see Table

15).

– Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit.

And select the following in the CR1 register:

– Set the ICIE bit to generate an interrupt after an

input capture.

– Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit.

When an input capture occurs:

– ICFi bit is set.

– The ICiR register contains the value of the free

running counter on the active transition on the

ICAPi pin (see Figure 27).

– A timer interrupt is generated if the ICIE bit is set

and the I bit is cleared in the CC register. Other-

wise, the interrupt remains pending until both

conditions become true.

Clearing the Input Capture interrupt request is

done in two steps:

1. Reading the SR register while the ICFi bit is set.

2. An access (read or write) to the ICiLR register.

Note: After reading the ICiHR register, transfer of

input capture data is inhibited until the ICiLR regis-

ter is also read.

The ICiR register always contains the free running

counter value which corresponds to the most re-

cent input capture.

During HALT mode, if at least one valid input cap-

ture edge occurs on the ICAPi pin, the input cap-

ture detection circuitry is armed. This does not set

any timer flags, and does not “wake-up” the MCU.

If the MCU is awoken by an interrupt, the input

capture flag will become active, and data corre-

sponding to the first valid edge during HALT mode

will be present.

MS Byte

LS Byte

ICiR

ICiHR

ICiLR

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