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LS1020A Arkusz danych(PDF) 21 Page - Freescale Semiconductor, Inc |
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LS1020A Arkusz danych(HTML) 21 Page - Freescale Semiconductor, Inc |
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21 / 71 page ![]() Architecture TWR-LS1021A Reference Manual, Rev. 0 2-6 Freescale Semiconductor Figure 2-4. Fuse programming power 2.3 Deep sleep control Not supported on TWR-LS1021A board. 2.4 Reset Reset signals to and from the LS1021A and other devices on TWR-LS1021A are managed by CPLD. Figure 2-5 shows an overview of the reset architecture. Figure 2-5. Reset architecture A reset controller (the reset sequencer) manages the collection of various reset triggers, and then asserts reset to internal and external devices as needed. Depending on the type of reset, not all registers and/or devices will be reset. In addition to functional reset choices, the reset controller manages the timing of the |
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