K6R1016C1D-UI10 datasheet(8/9 Pages) SAMSUNG

8 / 9 page

PRELIMINARY

Rev. 3.0

- 8 -

July 2004

PRELIMINARY

K6R1004V1D

CMOS SRAM

for AT&T

NOTES(WRITE CYCLE)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ;

A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of

write.

3. tCW is measured from the later of CS going low to end of write.

4. tAS is measured from the address valid to the beginning of write.

5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. Dout is the read data of the new address.

10.When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be

applied.

TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)

Address

tAW

tDW

tDH

Valid Data

Data in

Data out

High-Z

High-Z(8)

tCW(3)

tWP(2)

tAS(4)

tWC

tWR(5)

High-Z

tLZ

tWHZ(6)

FUNCTIONAL DESCRIPTION

* X means Don

′t Care.

Mode

I/O Pin

Supply Current

Not Select

High-Z

ISB, ISB1

Output Disable

High-Z

ICC

Read

DOUT

ICC

Write

DIN

ICC

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