WM8771 datasheet(21/44 Pages) WOLFSON

21 / 44 page

Product Preview

WM8771

PP Rev 2.0 December 2001

DSP LATE MODE

In DSP late mode, the MSB of DAC channel 1 left data is sampled by the WM8771 on the first BCLK

rising edge following a DACLRC rising edge. DAC channel 1 right and DAC channels 2, 3 and 4 data

follow DAC channel 1 left data (Figure 16).

DACLRC

BCK

DIN1

Input Word Length (IWL)

1/fs

CHANNEL 1

LEFT

n-1

LSB

MSB

n-1

CHANNEL 1

RIGHT

CHANNEL 2

LEFT

n-1

CHANNEL 4

RIGHT

NO VALID DATA

Figure 16 DSP Late Mode Timing Diagram – DAC data input

The MSB of the left channel ADC data is output on DOUT and changes on the same falling edge of

BCLK as the low to high ADCLRC transition and may be sampled on the rising edge of BCLK. The

right channel ADC data is contiguous with the left channel data (Figure 17).

ADCLRC

BCK

DOUT

Input Word Length (IWL)

1/fs

LEFT CHANNEL

n-1

LSB

MSB

n-1

RIGHT CHANNEL

NO VALID DATA

Figure 17 DSP Late Mode Timing Diagram – ADC data output

In both early and late DSP modes, DACL1 is always sent first, followed immediately by DACR1 and

the data words for the other 6 channels. No BCLK edges are allowed between the data words. The

word order is DAC1 left, DAC1 right, DAC2 left, DAC2 right, DAC3 left, DAC3 right, DAC4 left, DAC4

right.

WM8771 Arkusz danych(PDF) 21 Page - Wolfson Microelectronics plc

WM8771 Arkusz danych(HTML) 21 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

Arkusz danych Pobierz

Link URL