CS5510/11/12/13

8

DS337F3

SWITCHING CHARACTERISTICS - CS5511/13

Notes: 23. The internal oscillator in the CS5511/13 provides the master clock for performing conversions. Data is

retrieved from the serial port using the SCLK input pin.

24. The minimum SCLK rate for the CS5511/13 assumes that SCLK is logic 0 when idle. When data is being

read from the ADC, SCLK must be burst at a minimum rate of 10 kHz and with a minimum of a 10

percent duty cycle. Rates slower than this can potentially put the ADC into sleep as the sleep mode is

25. On the CS5511/13, the serial clock (SCLK) is used to transfer data from the CS5511/13. If SCLK is held

26. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF.

Parameter

Symbol

Min

Typ

Max

Unit

Internal Oscillator Timing

Internal Oscillator Frequency

(Note 23)

32

64

100

kHz

Internal Oscillator Drift Over Temperature

-

-

-0.02

-

%/°C

Serial Port Timing

Serial Clock Frequency

(Note 24)

SCLK

-

-

2

MHz

SCLK High to Enter Sleep

(Notes 24 and 25)

200

-

2000

µs

SCLK Low to Exit Sleep

(Notes 24 and 25)

10

-

-

µs

Rise Times

(Note 26)

CSB

SCLK

SDO

-

-

-

-

-

50

1.0

10

-

µs

µs

ns

Fall Times

(Note 26)

CSB

SCLK

SDO

-

-

-

-

-

50

1.0

10

-

µs

µs

ns

Serial Clock

Pulse Width High

Pulse Width Low

200

200

-

-

-

-

ns

ns

SDO Read Timing

CS

to Data Valid

--

150

ns

SCLK Falling to New Data Bit

--

150

ns

CS

Rising to SDO Hi-Z

--

150

ns

CS

Falling to SCLK Rising

200

-

-

ns